The invention refers to a power output stage with a load. The load is connected to a constant voltage source via a source-drain path of a field effect transistor (FET). See, for example, European Patent EP-A 0 236 1967, incorporated herein by reference.
If the field effect transistor is to be switched on, the potential at its gate terminal must be higher by a certain voltage than at its drain terminal.
The known circuit arrangement comprises a FET, whose sourcedrain path lies at a voltage source (circuit operating voltage) in line or in series with a load to be switched. One terminal of a capacitor is connected to a voltage source (charge circuit) via a diode, and to the gate terminal of the FET (control circuit) via another diode, whereby respectively one switch is arranged between the two diodes and the voltage source. The other terminal of the capacitor is supplied with a clocked dc voltage, if the FET is to be switched on. Simultaneously, the one switch must be closed and the other opened.